1. Field of the Invention
The present invention relates generally to a method of programming a multilevel nonvolatile memory cell which reduces the number of erase operations. More specifically the present invention relates to a method of consecutively programming a multilevel nonvolatile memory cell without a cell erase operation. The nonvolatile memory cell is typically a flash memory cell.
2. Description of the Related Art
Nonvolatile semiconductor memories use a variety of semiconductor memory cells designs. One type of nonvolatile memory cells uses an electrically isolated floating gate to trap charge. Such a type memory cell is referred to as a flash memory cell.
Flash memory is a new variation of a programmable nonvolatile memory, which is gaining favor because they can be erased and programmed (or reprogrammed) faster than the existing EPROMs (erasable programmable read-only memories), and because they use a simpler storage cell, thereby allowing more memory cells on a single chip. Further, in order to improve cost performance per transistor cell, it has been proposed for one cell to store more than two pieces of information (viz., more than one bit).
As is known in the art, a flash memory Is provided with a matrix array of one-transistor cells, each having a structure of the nature shown in FIG. 1, and which are arranged in rows and columns (as best illustrated in FIG. 3).
Prior to turning to the present invention it is deemed preferable to describe, with reference to FIGS. 1, 2A and 2B, a conventional flash memory and programming or reprogramming techniques.
In FIG. 1, a single transistor cell (depicted by numeral 10) is schematically shown in cross-section. The transistor cell 10 comprises a p-type silicon substrate 12 that carries, on the upper portion thereof, two n.sup.+ regions: one of which functions as a source 14 and the other of which acts as a drain 16. An n-channel is thus formed between the source 14 and the drain 16. A poly-silicon (for example) floating gate 18 is provided over the n channel via an insulation layer (silicon-dioxide layer (for example)) 20 (about 10 nm in thickness (for example)). A control gate 22 is situated over the floating gate 18 via another insulation layer 24 (about 25 nm (for example)). As is known in the art, electron tunneling can be used both to inject charge and to pull charge off the floating gate 18, while hot electron injection is another mechanism for inserting charge into the floating gate 18. Notations Vs, Vd, Vg and Vsub in FIG. 1 respectively designate voltage terminals that are coupled, via appropriate metal contacts (not shown), to the source 14, the drain 16, the gate 22, and the silicon substrate 12,
With a transistor cell storing only two values (viz., one bit), the threshold voltage of the cell is defined as the voltage on the floating gate 18 that is required to turn the transistor on. However, with a multilevel type transistor cell, the floating gate is selectively charged to one among a plurality of threshold voltages while programming or reprogramming. That is to say, the threshold voltages, depending on the respective values, determine the amount of currents each of which flows through the channel between the source and drain. The current is then converted to a corresponding voltage which is compared with an associated reference voltage, whereby the cell is capable of storing more than one bit.
Reference is made to FIG. 2A, which is a diagram describing one example of erase and reprogramming operations of the transistor cell shown in FIG. 1. It is assumed that the floating gate 18 (FIG. 1) has one of four threshold levels 1, 2, 3 and 4 that respectively correspond to 1 V, 2 V, 3 V and 4 V (merely by way of example). It is to be noted that each of the threshold levels 1, 2, 3 and 4 is with a predetermined range of voltages for each state, and thus, the above-mentioned concrete values of 1 V, 2 V, 3 V and 4 V are exemplary.
Prior to reprogramming, the cell is erased by bringing the voltage of the floating gate 18 to the lowest level (viz., LEVEL 1) irrespective of the previous threshold level. After completing the erase operation, the cell is reprogrammed to one of the threshold levels. In this case, If there is no need to change the first threshold voltage (LEVEL 1) of the floating gate 18, the reprogramming operation is not required.
On the other hand, another way to erase the cell is shown in FIG. 2B wherein the voltage of the floating gate 18 is set to the highest level (viz., LEVEL 4).
With both the cases shown in FIGS. 2A and 2B, it is understood that the erasing operation is absolutely necessary before each reprogramming.
During the erase operation, a high electric filed strength is developed in the insulation layer 20 in order to impel electrons already injected into the floating gate 18 (as in the case shown in FIG. 2A), or in order to inject electrons to raise the potential of the gate 18 (as in the case shown in FIG. 2B). As a result, the layer 20 is undesirably subjected to electric stress each time the erasing is performed. That is, the repeatedly applied electric stress prior to each programming leads to the deterioration of the cell's performance characteristics and further, results in shortening the longevity of memory cell. Further, the time period necessary for erasing is much larger than that for programming, which undesirably lowers the operation speed of flash memory.
It is therefore highly preferable that a plurality of consecutive programming operations can be carried out with the very minimum of erasing operations.